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rev.1.01, nov.18. 2004, page 1 of 19 r1lv1616h-i series wide temperature range version 16 m sram (1-mword 16-bit / 2-mword 8-bit) rej03c0195-0101 rev.1.01 nov.18.2004 description the r1lv1616h-i series is 16-mbit static ram organized 1-mword 16-bit / 2-mword 8-bit. r1lv1616h-i series has realized higher density, hi gher performance and low power consumption by employing cmos process technology (6-transistor memory cell). it offers low power standby power dissipation; therefore, it is suitable for battery backup systems. it is packaged in 48-pin plastic tsopi for high density surface mounting. features ? single 3.0 v supply: 2.7 v to 3.6 v ? fast access time: 45/55 ns (max) ? power dissipation: ? active: 9 mw/mhz (typ) ? standby: 1.5 w (typ) ? completely static memory. ? no clock or timing strobe required ? equal access and cycle times ? common data input and output. ? three state output ? battery backup operation. ? 2 chip selection for battery backup ? temperature range: ? 40 to +85 c ? byte function ( 8 mode) available by byte# & a-1.
r1lv1616h-i series rev.1.01, nov.18. 2004, page 2 of 19 ordering information type no. access time package R1LV1616HSA-4LI 45 ns 48-pin plastic tsopi (48p3r-b) r1lv1616hsa-4si 45 ns r1lv1616hsa-5si 55 ns
r1lv1616h-i series rev.1.01, nov.18. 2004, page 3 of 19 pin arrangement 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 a15 a14 a13 a12 a11 a10 a9 a8 a19 nc we# cs2 nu ub# lb# a18 a17 a7 a6 a5 a4 a3 a2 a1 a16 byte# v i/o15/a-1 i/o7 i/o14 i/o6 i/o13 i/o5 i/o12 i/o4 v i/o11 i/o3 i/o10 i/o2 i/o9 i/o1 i/o8 i/o0 oe# v cs1# a0 cc ss ss (top view) 48-pin tsop
r1lv1616h-i series rev.1.01, nov.18. 2004, page 4 of 19 pin description (tsop) pin name function a0 to a19 address input (word mode) a-1 to a19 address input (byte mode) i/o0 to i/o15 data input/output cs1# ( cs1 ) chip select 1 cs2 chip select 2 we# ( we ) write enable oe# ( oe ) output enable lb# ( lb ) lower byte select ub# ( ub ) upper byte select byte# ( byte ) byte enable v cc power supply v ss ground nc no connection nu* 1 not used (test mode pin) note: 1. this pin should be connected to a ground (v ss ), or not be connected (open).
r1lv1616h-i series rev.1.01, nov.18. 2004, page 5 of 19 block diagram (tsop) ? i/o0 i/o15 cs2 byte# we# oe# a17 a7 a6 a2 a0 v v cc ss row decoder memory matrix 8,192 x 128 x 16 8,192 x 256 x 8 column i/o column decoder input data control control logic a1 a15 a14 a13 a12 a11 a10 a9 a8 a18 a16 a19 a4 a5 cs1# lb# ub# a3 lsb msb msb lsb a-1
r1lv1616h-i series rev.1.01, nov.18. 2004, page 6 of 19 operation table (tsop) byte mode cs1# cs2 we# oe# ub# lb# byte# i/o0 to i/o7 i/o8 to i/o14 i/o15 operation h l high-z high-z high-z standby l l high-z high-z high-z standby l h h l l dout high-z a-1 read l h l l din high-z a-1 write l h h h l high-z high-z high-z output disable note: h: v ih , l: v il , : v ih or v il word mode cs1# cs2 we# oe# ub# lb# byte# i/o0 to i/o7 i/o8 to i/o14 i/o15 operation h h high-z high-z high-z standby l h high-z high-z high-z standby h h h high-z high-z high-z standby l h h l l l h dout dout dout read l h h l h l h dout high-z high-z lower byte read l h h l l h h high-z dout dout upper byte read l h l l l h din din din write l h l h l h din high-z high-z lower byte write l h l l h h high-z din din upper byte write l h h h h high-z high-z high-z output disable note: h: v ih , l: v il , : v ih or v il
r1lv1616h-i series rev.1.01, nov.18. 2004, page 7 of 19 absolute maximum ratings parameter symbol value unit power supply voltage relative to v ss v cc ? 0.5 to +4.6 v terminal voltage on any pin relative to v ss v t ? 0.5 * 1 to v cc + 0.3 * 2 v power dissipation p t 1.0 w storage temperature range tstg ? 55 to +125 c storage temperature range under bias tbias ? 40 to +85 c notes: 1. v t min: ? 2.0 v for pulse half-width 10 ns. 2. maximum voltage is +4.6 v. dc operating conditions parameter symbol min typ max unit note supply voltage v cc 2.7 3.0 3.6 v v ss 0 0 0 v input high voltage v ih 2.2 ? v cc + 0.3 v input low voltage v il ? 0.3 ? 0.6 v 1 ambient temperature range ta ? 40 ? +85 c note: 1. v il min: ? 2.0 v for pulse half-width 10 ns.
r1lv1616h-i series rev.1.01, nov.18. 2004, page 8 of 19 dc characteristics parameter symbol min typ max unit test conditions * 2 input leakage current |i li | ? ? 1 a vin = v ss to v cc output leakage current |i lo | ? ? 1 a cs1# = v ih or cs2 = v il or oe# = v ih or we# = v il or lb# = ub# = v ih , v i/o = v ss to v cc operating current i cc ? ? 20 ma cs1# = v il , cs2 = v ih , others = v ih / v il , i i/o = 0 ma average operating current i cc1 (read) ? 22 * 1 35 ma min. cycle, duty = 100%, i i/o = 0 ma, cs1# = v il , cs2 = v ih , we# = v ih , others = v ih /v il i cc1 ? 30 * 1 50 ma min. cycle, duty = 100%, i i/o = 0 ma, cs1# = v il , cs2 = v ih , others = v ih /v il i cc2 * 3 (read) ? 3 * 1 8 ma cycle time = 70 ns, duty = 100%, i i/o = 0 ma, cs1# = v il , cs2 = v ih , we# = v ih , others = v ih /v il address increment scan or decrement scan i cc2 * 3 ? 20 * 1 30 ma cycle time = 70 ns, duty = 100%, i i/o = 0 ma, cs1# = v il , cs2 = v ih , others = v ih /v il address increment scan or decrement scan i cc3 ? 3 * 1 8 ma cycle time = 1 s, duty = 100%, i i/o = 0 ma, cs1# 0.2 v, cs2 v cc ? 0.2 v v ih v cc ? 0.2 v, v il 0.2 v standby current i sb ? 0.1 * 1 0.5 ma cs2 = v il -4si -5si i sb1 ? 0.5 * 1 8 a standby current -4li i sb1 ? 0.5 * 1 25 a 0 v vin (1) 0 v cs2 0.2 v or (2) cs1# v cc ? 0.2 v, cs2 v cc ? 0.2 v or (3) lb# = ub# v cc ? 0.2 v, cs2 v cc ? 0.2 v, cs1# 0.2 v average value output high voltage v oh 2.4 ? ? v i oh = ? 1 ma v oh v cc ? 0.2 ? ? v i oh = ? 100 a output low voltage v ol ? ? 0.4 v i ol = 2 ma v ol ? ? 0.2 v i ol = 100 a
r1lv1616h-i series rev.1.01, nov.18. 2004, page 9 of 19 notes: 1. typical values are at v cc = 3.0 v, ta = +25 c and not guaranteed. 2. byte# v cc ? 0.2 v or byte# 0.2 v 3. i cc2 is the value measured while the valid addr ess is increasing or decreasing by one bit. word mode: lsb (least significant bit) is a0. byte mode: lsb (least significant bit) is a-1. capacitance (ta = +25 c, f = 1.0 mhz) parameter symbol min typ max unit test conditions note input capacitance cin ? ? 8 pf vin = 0 v 1 input/output capacitance c i/o ? ? 10 pf v i/o = 0 v 1 note: 1. this parameter is sampled and not 100% tested.
r1lv1616h-i series rev.1.01, nov.18. 2004, page 10 of 19 ac characteristics (ta = ? 40 to +85 c, v cc = 2.7 v to 3.6 v, unless otherwise noted.) test conditions ? input pulse levels: v il = 0.4 v, v ih = 2.4 v ? input rise and fall time: 5 ns ? input and output timing reference levels: 1.4 v ? output load: see figures (including scope and jig) 50pf dout rl=500 ? 1.4 v
r1lv1616h-i series rev.1.01, nov.18. 2004, page 11 of 19 read cycle r1lv1616h-i -4si, -4li -5si parameter symbol min max min max unit notes read cycle time t rc 45 ? 55 ? ns address access time t aa ? 45 ? 55 ns chip select access time t acs1 ? 45 ? 55 ns t acs2 ? 45 ? 55 ns output enable to output valid t oe ? 30 ? 35 ns output hold from address change t oh 10 ? 10 ? ns lb#, ub# access time t ba ? 45 ? 55 ns chip select to output in low-z t clz1 10 ? 10 ? ns 2, 3 t clz2 10 ? 10 ? ns 2, 3 lb#, ub# enable to low-z t blz 5 ? 5 ? ns 2, 3 output enable to output in low-z t olz 5 ? 5 ? ns 2, 3 chip deselect to output in high-z t chz1 0 20 0 20 ns 1, 2, 3 t chz2 0 20 0 20 ns 1, 2, 3 lb#, ub# disable to high-z t bhz 0 15 0 20 ns 1, 2, 3 output disable to output in high-z t ohz 0 15 0 20 ns 1, 2, 3 write cycle r1lv1616h-i -4si, -4li -5si parameter symbol min max min max unit notes write cycle time t wc 45 ? 55 ? ns address valid to end of write t aw 45 ? 50 ? ns chip selection to end of write t cw 45 ? 50 ? ns 5 write pulse width t wp 35 ? 40 ? ns 4 lb#, ub# valid to end of write t bw 45 ? 50 ? ns address setup time t as 0 ? 0 ? ns 6 write recovery time t wr 0 ? 0 ? ns 7 data to write time overlap t dw 25 ? 25 ? ns data hold from write time t dh 0 ? 0 ? ns output active from end of write t ow 5 ? 5 ? ns 2 output disable to output in high-z t ohz 0 15 0 20 ns 1, 2 write to output in high-z t whz 0 15 0 20 ns 1, 2
r1lv1616h-i series rev.1.01, nov.18. 2004, page 12 of 19 byte control r1lv1616h-i -4si, -4li -5si parameter symbol min max min max unit notes byte# setup time t bs 5 ? 5 ? ms byte# recovery time t br 5 ? 5 ? ms notes: 1. t chz , t ohz , t whz and t bhz are defined as the time at whic h the outputs achieve the open circuit conditions and are not referr ed to output voltage levels. 2. this parameter is sampled and not 100% tested. 3. at any given temper ature and voltage condition, t hz max is less than t lz min both for a given device and from device to device. 4. a write occurs during the ov erlap of a low cs1#, a high cs2, a low we# and a low lb# or a low ub#. a write begins at the latest transit ion among cs1# going low, cs2 going high, we# going low and lb# going low or ub# going low. a wr ite ends at the earliest transition among cs1# going high, cs2 going low, we# going high and lb# going high or ub# going high. t wp is measured from the beginning of write to the end of write. 5. t cw is measured from the later of cs1# going low or cs2 going high to the end of write. 6. t as is measured from the address va lid to the beginning of write. 7. t wr is measured from the earliest of cs1# or we# going high or cs2 going low to the end of write cycle.
r1lv1616h-i series rev.1.01, nov.18. 2004, page 13 of 19 timing waveform read cycle* 1 t aa t acs1 t acs2 t clz2 t clz1 t blz t ba t oh t rc valid data valid address high impedance cs1# cs2 lb#, ub# oe# t olz t oe t chz1 t chz2 t bhz t ohz address * 2 dout * 3 notes: 1. byte# > v cc ? 0.2 v or byte# < 0.2 v 2. word mode: a0 to a19 byte mode: a-1 to a19 3. word mode: i/o0 to i/o15 byte mode: i/o0 to i/o7
r1lv1616h-i series rev.1.01, nov.18. 2004, page 14 of 19 write cycle (1)* 1 (we # clock) we# t wc t aw t wp t wr t cw t cw t bw t as t ow t whz t dw t dh valid address valid data cs1# lb#, ub# high impedance cs2 address * 2 dout * 3 din * 3 notes: 1. byte# > v cc ? 0.2 v or byte# < 0.2 v 2. word mode: a0 to a19 byte mode: a-1 to a19 3. word mode: i/o0 to i/o15 byte mode: i/o0 to i/o7
r1lv1616h-i series rev.1.01, nov.18. 2004, page 15 of 19 write cycle (2)* 1 (cs1#, cs2 clock, oe# = v ih ) address * 2 we# t wc t aw t wp t wr t cw t cw t bw t as t dw t dh valid address valid data lb#, ub# dout * 3 din * 3 high impedance cs2 cs1# notes: 1. byte# > v cc ? 0.2 v or byte# < 0.2 v 2. word mode: a0 to a19 byte mode: a-1 to a19 3. word mode: i/o0 to i/o15 byte mode: i/o0 to i/o7 t as
r1lv1616h-i series rev.1.01, nov.18. 2004, page 16 of 19 write cycle (3)* 1 (lb#, ub# clock, oe # = v ih ) address we# t wc t aw t wp t cw t cw t bw t bw t wr t dw t dh valid address ub# (lb#) high impedance cs2 cs1# t as lb# (ub#) dout din-ub (din-lb) din-lb (din-ub) valid data t dw t dh valid data note: 1. byte# > v cc ? 0.2 v
r1lv1616h-i series rev.1.01, nov.18. 2004, page 17 of 19 byte control (tsop) t bs t br cs2 byte# cs1#
r1lv1616h-i series rev.1.01, nov.18. 2004, page 18 of 19 low v cc data retention characteristics (ta = ? 40 to +85 c) parameter symbol min typ max unit test conditions * 2, 3 v cc for data retention v dr 1.5 ? 3.6 v vin 0 v (1) 0 v cs2 0.2 v or (2) cs2 v cc ? 0.2 v, cs1# v cc ? 0.2 v or (3) lb# = ub# v cc ? 0.2 v, cs2 v cc ? 0.2 v, cs1# 0.2 v -4si -5si i ccdr ? 0.5 * 1 8 a data retention current -4li i ccdr ? 0.5 * 1 25 a v cc = 3.0 v, vin 0 v (1) 0 v cs2 0.2 v or (2) cs2 v cc ? 0.2 v, cs1# v cc ? 0.2 v or (3) lb# = ub# v cc ? 0.2 v, cs2 v cc ? 0.2 v, cs1# 0.2 v average value chip deselect to data retention time t cdr 0 ? ? ns see retention waveforms operation recovery time t r 5 ? ? ms notes: 1. typical values are at v cc = 3.0 v, ta = +25 c and not guaranteed. 2. byte# v cc ? 0.2 v or byte# 0.2 v 3. cs2 controls address buffer, we# buffer, cs1# buffer, oe# buffer, lb#, ub# buffer and din buffer. if cs2 controls data ret ention mode, vin levels (address, we#, oe#, cs1#, lb#, ub#, i/o) can be in the high impedance state. if cs1# controls data retenti on mode, cs2 must be cs2 v cc ? 0.2 v or 0 v cs2 0.2 v. the other input levels (address, we#, oe#, lb#, ub#, i/o) can be in the high impedance state.
r1lv1616h-i series rev.1.01, nov.18. 2004, page 19 of 19 low v cc data retention timing waveform (1) (cs1 # controlled) cc v 2.7 v 2.2 v 0 v cs1# t cdr t r cs1# v ? 0.2 v cc dr v data retention mode low v cc data retention timing waveform (2) (cs2 controlled) cc v 2.7 v 0.6 v 0 v cs2 cdr t r 0 v cs2 0.2 v dr v data retention mode t < < low v cc data retention timing waveform (3) (lb #, ub # controlled) cc v 2.7 v 2.2 v 0 v lb#, ub# t cdr t r lb#, ub# v ? 0.2 v cc dr v data retention mode
revision history r1lv1616h-i series data sheet contents of modification rev. date page description 1.00 apr. 22, 2004 ? initial issue 1.01 nov. 18, 2004 ? addition of 2-mword 8-bit function
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